1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, incorporated by reference herein.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009, incorporated by reference herein. The structure described in Katsumata et al. includes a vertical NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a so-called gate all around cell at each layer.
FIG. 1 is a horizontal cross-section of a column of a pipe-shaped BiCS flash cells, such as described in the Katsumata et al. publication, at the level of a word line. The structure includes a pillar 15 having a center core 110 of semiconductor material which extends vertically through a stack of word line layers. The core 110 may have a seam 111 through the middle that arises from the deposition technique. A dielectric charge trapping structure comprising for example a first layer 112 of silicon oxide, a layer 113 of silicon nitride and a second layer 114 of silicon oxide (referred to as ONO), or another multilayer dielectric charge trapping structure surrounds the core 110. A gate all-around word line is intersected by the pillar. A frustum of the pillar at each layer combines with the gate all-around word line structure at that layer, to form a memory cell.
FIG. 2 is a perspective view of a 3D semiconductor device. It comprises a multilevel stack of word line conductive layers 11, each parallel to the substrate (not shown); a plurality of pillars 15 oriented orthogonally to the substrate, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers; and a plurality of string select lines (SSLs) 12 oriented parallel to the substrate and above the conductive layers 11, each of the string select lines intersecting a respective row of the pillars. Each intersection of a pillar and a string select line defines a string select gate (SSG) of the pillar. The structure also includes ground select lines (GSL) 13 (also sometimes called lower select lines especially in embodiments, like FIG. 2, where they are located at the lower end of a pillar) oriented parallel to the substrate and forming a layer below the word line conductive layers 11. Each intersection of a pillar and a ground select line 13 defines a ground select gate (GSG) (also sometimes called a lower select gate (LSG) of the pillar. A common source line (CSL) 10 is formed in a layer parallel to the substrate and below the GSLs. The structure also includes a plurality of parallel bit line conductors 20 in a layer parallel to the substrate and above the string select lines. Each of the bit line conductors superposes a respective column of the pillars, and each of the pillars underlies one of the bit line conductors. The pillars may be constructed as described above with respect to FIG. 1.
The illustration of FIG. 2 shows two blocks of memory cells laterally, due to the lateral split between two portions 26A and 26B of the word line conductive layers 11. For example, word line 26A defines one block of memory cells, whereas word line 26B defines a second block of memory cells. Similarly, the illustration shows two corresponding ground select lines 28A and 28B.
FIG. 3 is a top view of a portion of the structure of FIG. 2. As can be seen, a word line such as 26A intersects only some of the pillars in the overall structure; each word line 26A or 26B defines a block of memory cells. Thus to read data from a particular block of the memory, control circuitry activates a word line 26A, 26B to select a block of cells and a particular layer of the stack, and further activates a string select line 12 to select a particular row. A ground select gate is activated as well. A row of cells is then read out in parallel via the bit line conductors 20 into a page buffer (not shown). (“Activate”, as used herein, means to apply a particular bias so as to give effect to the connected cells or switches. The bias may be high or low, depending on the memory design.) Depending on the product specification and design, the page buffer may hold two or more rows of data, in which case a full page read operation would involve successive activation of two or more SSLs 12.
While 3D stacking memory structures hold the promise of greatly increased memory density, they also introduce significant process challenges because, among other things, of the need to etch very deep holes through many layers. Such deep holes have to be made wider, and have to be placed at greater center-to-center distance from each other laterally, in order to meet process windows. As fabrication processes improve, capacity may be increased not only by increasing the number of word line planes in the stack, but also by reducing the spacing between the pillars. FIG. 4 is a top view of a scaled down structure in which both the number of bit lines 20 in a block and the number of SSLs 12 in the block have been increased. Not only does the cost decrease, but increased read/write data rate can be achieved as well because the larger number of bit lines 20 means increased parallel operation. On the other hand, the increased number of SSLs 12 means more cells will suffer Vpass disturb due to word line select. Unit cell capacitance also increases with the number of SSLs 12, thereby increasing power consumption and slowing device operation.
Increasing bit density by increasing the number of word line conductive layers 11 in the stack also has downsides, even aside from the expected process challenges of increased numbers of layers. In FIG. 2 it can be seen that a typical arrangement has a stepped contact structure to the word line conductive layers 11. Deep etches are made through the structure in order to form contacts 22 to connect the conductive layers 11 to metal interconnects 24 above. These contacts 22 are also shown symbolically in the top view of FIG. 4. In a typical design, the number of rows of pillars 15 in a block is at least as great as the number of contacts 22, and hence memory layers. See, for example, Komori, Y., et al., “Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device,” Electron Devices Meeting, 2008, IEDM 2008, IEEE International, vol., no., pp. 1-4, 15-17 (December 2008) at 2, incorporated herein by reference. Thus increasing the number of memory layers also increases the number of SSLs 12, and again increases power consumption and slows device operation.
An opportunity therefore arises to create robust solutions to the problem of increasing bit density of 3D memory structures while reducing the negative impacts that such increases tend to cause. Better chip yields, and denser, and more powerful circuits, components and systems may result.